I already gave an explanation about everything in general about the Acorn RiscPC and the RiscOS at the previous page, so this one should be for people who are not only users but know more about computers.
The ARM Risc-processor
What RISC stands for and what it means I already explained, that's why I will go into the StrongARM in detail.
The used StrongARM is a Risc-processor with an Onboard-cache. It is smaller and cooler than the usual CISC-processors (CISC stands for Complex Instruction Set CPU), what means that no cooling in the motherboard is necessary. It gets - without a cooling - just room temperature and consumes with 202 Mhz clock frequency only 0.9 watts!
Although on the previous page there are already things about graphics there are still some things left to say.
The graphic chip is a 64 bit co-processor with about 157MB/s data rate.
People who work with graphics (on the way, there is a very popular and well-known Risc-computer in the branch, most of the people just don't know it is one) would surely wonder about what an Acorn RiscPC is able to do.
The Acorn Risc has a very effective Interpreter-BASIC which is implemented in RiscOS. It works without any linking and compiling.
You just open a window and start the programming, then you start the result with a double-click - that's it.
The BASIC is even quick enough for 3-D-graphics.
You can look into every program or file via implemented editor, you just click it with held shift-button. Then you can change it as you want (at least a minimal knowledge naturally would be reasonable!).
The memory-space you work with can be assigned to the applications as you want. So you can speed up for example the copying of files.
For C-freaks there are of course the relevant applications available.
Who thinks that BASIC programs are too slow or simple, will probably be interested in the Assembler which is implemented in BASIC. In a BASIC program (no matter where) a part of the program can be written in Assembler without any problems. This part can be written in an own file (via a BASIC command) and it's called up from there, or it could stay in the BASIC and be started there.
operating system routines which relieve the programmer a huge part of the work. They can be called up easily by name and the corresponding parameters - no matter from which program-plain.
The 30 basic commands I mentioned before can be supplied with different conditions as well as with the permission to influence the flags.(There is a lot of space in the instruction-code with 32 bit...)
This is saving masses of branches as the execution of the commands depends on the conditions (or the flags).
So the extra setting and erasing of flags is mostly getting superfluously.
There are 18 conditions in the assembler language of the ARM, for example EQ, NE, CS, CC...
The Risc CPU needs instead of up to 35 clock frequencies only 3 of them, and this because of the hardware-implementing of the codes for the execution of program structures.
Of course this is not possible for all structures - the CPU can't work miracles.
Nevertheless, a moving command (no matter how many bits) to the left or right needs one clock-cycle only! So, do you wonder when RISCs - at the same clock frequency - are so much faster with these tricks?
The ARM-processor has 16 pieces of 32 bit-registers at its disposal. They are called from R0 up to R15 and you can use them as you want except for the last two.
R15 is the address-counter and R14 contents the return-address of a branch-command - but only if it's wished.
So the branches (with a condition of course) can be executed as subroutines, and that's why an own command for the execution of those is missing - that's RISC!
Some segments are not existing because this would be superfluous...
The execution of commands is dependend on a condition, like for example set zero flag - besides the influence on the flags of the status register can be allowed or forbidden, and all of this in only one command word.
MOV EQ S R0,R1,LSR#4
This is one command and gets executed in one clock-frequency.
The meaning: When the z-flag is set (EQ), so bring (MOV) register 1 into register 0, multiply it there with 8 (LSR#4 = rotate to the left by four bit) and influence the status-register according to the result.
When the z-flag is not set, then the command gets ignored and the next one gets decoded. One command, one clock-cycle!
Branch-commands (which branch in an address-area of 64 MB) are needed seldomly because of this conditioned commands. This optimates the use of the Onboard-cache of the ARM of course.